In present semiconductor technology, CMOS devices, such as n-FETs and p-FETs, are typically fabricated upon semiconductor wafers that each has a substrate surface oriented along one of a single set of equivalent crystal planes of the semiconductor material (e.g., Si) that forms the substrate. In particular, most of today's semiconductor devices are built upon silicon wafers having wafer surfaces oriented along one of the {100} crystal planes of silicon.
Electrons are known to have a high mobility along the {100} crystal planes of silicon, but holes are known to have high mobility along the {110} crystal planes of silicon. Specifically, hole mobility values along the {100} planes are roughly about 2 to 4 times lower than the corresponding electron mobility values along such planes. On the other hand, hole mobility values along the {110} silicon surfaces are about 2 times higher than those along the {100} silicon surfaces, but electron mobility along the {110} surfaces are significantly degraded compared to those along the {100} surfaces.
As can be deduced from the above, the {110} silicon surfaces are optimal for forming p-FET devices due to the excellent hole mobility along the {110} planes, which leads to higher drive currents in the p-FETs. However, such surfaces are completely inappropriate for forming n-FET devices. The {100} silicon surfaces instead are optimal for forming n-FET devices due to the enhanced electron mobility along the {100} planes, which results in higher drive currents in the n-FETs.
In view of the above, there is a need for providing a semiconductor substrate having different surface orientations (i.e., hybrid surface orientations) that provide optimal performance for a specific device.
A need also exists to provide a method to form an integrated semiconductor device formed on a substrate with hybrid surface orientations, while the integrated semiconductor device comprises at least an n-FET and a p-FET having hybrid channel orientations, i.e., the n-FET channel is oriented along a first set of equivalent crystal planes that provide relatively higher electron mobility, and the p-FET channel is oriented along a second, different set of equivalent crystal planes that provide relatively higher hole mobility.